The scaling of VLSI circuits is a constant effort. Smaller integrated circuits allow more devices to be formed in one semiconductor chip. Additionally, power consumption and performance are also improved. With circuits becoming smaller and faster, improvement in device driving current is becoming more important, which can be increased by improving carrier mobility. Among efforts made to enhance carrier mobility, forming a stressed channel region is a known practice. The performance of a MOS device can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length without adding complexity to circuit fabrication or design.
Research has revealed that a bi-axial, in-plane tensile stress field can improve NMOS performance, and a compressive stress parallel to the channel length direction can improve PMOS device performance. A commonly used method for applying stress to the channel region is forming a stressed contact etch stop layer (CESL) on a MOS device. The stressed CESLs introduce stress into the channel region. Therefore, the carrier mobility is improved. Typically, thick CESLs are preferred as thicker CESLs apply greater stresses in the channel regions of MOS devices.
With the scaling of integrated circuits, however, such a method encounters a problem. When devices become smaller, the distance between devices decreases. The subsequently performed gap-filling and contact etch processes suffer problems accordingly. The gap-filling problem may be explained using FIG. 1. A gap forms between two neighboring MOS devices 2 and 4, and the aspect ratio of the gap may be defined as the ratio of height H to width W. With a high aspect ratio for the gap, voids may be formed during the subsequent formation of an inter-layer dielectric layer. The voids may cause difficulty in subsequent processes, and may cause problems, such as short circuits, if the voids are filled with conductive materials.
A further problem is explained using FIGS. 2A and 2B. Referring to FIG. 2A, two MOS devices 12 and 14 are formed adjacent each other. The gap between MOS devices 12 and 14 has a height H and a width W. A CESL 16 is formed over the MOS devices 12 and 14. The region 18 between the MOS devices 12 and 14 is available for forming contact plugs (not shown). Since CESL 16 inside region 18 is relatively flat, the subsequent contact-etch process, during which an inter-layer dielectric layer (not shown) and a CESL 16 are etched, is relatively easy.
If the distance between MOS devices 12 and 14 are decreased, as shown in FIG. 2B, the width W is also reduced. This causes a narrowing of the region 18. If a CESL 16 with a same thickness as in FIG. 2A is formed, the CESL 16 in region 18 will experience great thickness variation. As a result, the subsequent contact-etch process experiences difficulty, and over-etch may occur at one location and under-etching may occur at another. To reduce such an effect, the thickness of the CESL 16 is preferably reduced, which in turn limits the stress applied by CESL 16.
A semiconductor device that may overcome the previously discussed deficiencies of the prior art is thus needed.